1. Field of the Invention
The present invention relates to a memory synchronization method and a refresh control circuit for synchronizing timing for refresh of multiple ranks of mounted memory.
2. Description of the Related Art
There is a conventionally known fault-tolerant computer which multiplexes (double or triple for instance) components constituting hardware of the computer such as a CPU (Central Processing Unit), a memory, a disk, a network, a power supply and the like in a computer system to allow uninterrupted operation without stopping the computer system even if one of the components is at fault.
In the case of the fault-tolerant computer, there are a lockstep method wherein multiplexed mutual components constantly executes the same operation in the same timing and in synchronization and a method of allowing certain components to go out of synchronization by getting processing results together and making a comparison. These are described in Japanese Patent Laid-Open No. 1999-338832 and Japanese Patent Laid-Open No. 2004-110803 for instance.
To implement a complete lockstep of a CPU bus in this connection, processing for the components thereunder needs to be synchronized. In particular, access to the memory requires high-speed processing, and so it is desirable that complete lockstep operation be also performed between the CPU and the memory.
The memory used for a general computer system is a type called DRAM (Dynamic Random Access Memory), which requires electric charge to be periodically replenished by a refresh operation in order to hold memory contents. Even when the access from the CPU to the memory is in synchronization, the timing of data returned from the memory to the CPU may be off if the timing of refresh is off.
Factors behind the off-timing refresh will be described.
FIG. 1 is a block diagram of a circuit for periodically generating the refresh.
As for the circuit shown in FIG. 1, a refresh counter 1 counts the timing for performing the refresh. It becomes an initial value 0 under an asynchronous reset signal RST which is asynchronous, and operates in synchronization with a clock signal CLK. It can also be the initial value 0 under a synchronous reset signal. In FIG. 1, a refresh counter asynchronous reset signal 112 is inputted. A refresh interval register 2 is a register for setting an interval of the refresh. As for the interval of the refresh, a maximum period (tREF I) is decided according to the kind of memory to be used. For instance, it is 7.8 μs or 3.9 μs in the case of DDR SDRAM and DDR2 SDRAM prescribed by JEDEC. In the case of performing the refresh with a period of 7.8 μs when a frequency of the clock signal CLK is 200 MHz for instance, the value of the refresh interval register 2 is set at 1560 (7.8 μs/5 ns). A refresh interval comparison portion 4 compares the value of the refresh counter 1 to the value of the refresh interval register 2 and outputs “1” if they match. A memory command generating portion 7 adjusts the refresh and other requests (omitted in FIG. 1) and issues an optimal command to a memory bus.
FIG. 2 is a timing chart showing operation of the circuit shown in FIG. 1.
The refresh counter 1 is initialized to 0 under the asynchronous reset signal RST, and the refresh counter 1 counts it up in synchronization with the clock signal CLK.
If the value of the refresh counter 1 matches with the value of the refresh interval register 2, the refresh counter asynchronous reset signal 112 becomes active and announces a start of the refresh. The refresh counter 1 is initialized to 0 by the refresh counter asynchronous reset signal 112 so as to continue the count.
Wait REF to Req Busy shown in FIG. 2 are internal signals of the memory command generating portion 7. When the refresh counter asynchronous reset signal 112 is asserted, Req Busy is active so that the refresh cannot be started at once and the Wait REF signal becomes active. If Req Busy is released, OK REF is asserted and a refresh command is issued to the memory.
Therefore, the timing for issuing the refresh command to the memory is based on the timing of the refresh counter 1. To synchronize refresh timing of multiplexed memory, it is necessary to synchronize the counter for deciding a refresh period.
FIG. 3 is a diagram showing the fault-tolerant computer doubled by a board A and a board B. Hereunder, a description will be given as to a problem in the case of synchronizing the timing of memory refresh of the fault-tolerant computer shown in FIG. 3.
FIG. 4 is a diagram showing the problem due to the timing of an asynchronous reset of the fault-tolerant computer shown in FIG. 3.
In the case where the asynchronous reset is simultaneously performed to each of the board A and the board B shown in FIG. 3, a characteristic of a reset route of each board may be a little different or a setup or a hold may not be satisfied even when it is completely simultaneous. Therefore, the counter values may be different depending on the timing of the asynchronous reset as shown in FIG. 4.
FIG. 5 is a diagram showing the operation when restarting the board A on the fault-tolerant computer shown in FIG. 3.
In the case of the fault-tolerant computer, a module at fault is separated and remounted. In this case, however, the module in operation is not initialized by asynchronous reset so that the counter values do not match as shown in FIG. 5.
FIG. 6 is a diagram showing order of commands issued to the memory bus in the case where the timing of a refresh request is off and synchronized memory reads compete in the memory command generating portion 7 in the fault-tolerant computer shown in FIG. 3.
As shown in FIG. 6, Read is asserted in the same timing on the board A and the board B. In this case, Start REF timing of the board A is 1 clock behind Start REF of the board B. In the case of the board A, Read and Start REF are simultaneous. If priority of Read is high, a read command is issued to the memory, and precharge (in the case where a refresh subject rank is open) and refresh are subsequently issued respectively.
On the board B, Start REF was asserted before Read so that a refresh process is performed first and the read is subsequently issued. If it is the read to the same rank as the refresh, the read command can be issued by performing activation after a sufficient time (t RFC) following the refresh command as shown in FIG. 6.
Therefore, there are the cases where, if the refresh request is different just by 1 clock, the response of the data which is read from the memory is different by dozens of clocks or over.
Various techniques are conceived as to the above-mentioned memory refresh operation. These are described in Japanese Patent Laid-Open No. 1995-73059, Japanese Patent Publication No. 1995-9625 and Japanese Patent Laid-Open No. 2000-330812 for instance.
Although Japanese Patent Laid-Open No. 1995-73059 and Japanese Patent Publication No. 1995-9625 describe a method of hiding the refresh operation from other memory access by delaying the refresh operation, there is a problem that the lockstep operation cannot be assured in the case where the counter value for deciding the refresh timing is different by the board.
There is also a problem that performance degradation of the memory access occurs in the system which assures the lockstep by waiting for the timing for returning read data to the module having made a request to the memory.
What is described in Japanese Patent Laid-Open No. 2000-330812 merely times a refresh circuit when initializing the memory, and no consideration is given to the access from a high order module for exerting refresh control over multiple memory modules.